EDN

Macraigor unveils USB 2.0 JTAG debug interfaces

Macraigor Systems LLC's usb2Demon and usb2Sprite, two new USB 2.0 JTAG debug interface devices are identical in functionality but differ in speed to provide embedded developers with flexibility in ...
EDN

Using ATmega644 on JTAG Debugger

This debugger was implemented and designed for the ATmega644 which utilizes its JTAG interface for communication as it sets breakpoints and access registers and memory in order to control program ...
Bleeping Computer

Intel CPUs Can Be Pwned via USB Port and Debugging Interface

The debugging interface is JTAG (Joint Test Action Group), a debugging framework that has been included for many years with Intel chipsets. JTAG works under the software level, allowing engineers, ...
Digital Trends

Intel responds to report about hackers gaining access to a debugging interface

Intel responded to a claim about hackers gaining hardware-level access to PCs sporting its sixth- and seventh-generation processors. The claim was made during a presentation at the 33rd annual Chaos ...
Embedded

Defining standard Debug Interface Socket requirements for OCP-Compliant multicore SoCs: Part 1

Enabling a robust on-chip debug capability is being recognized as animportant Design for Debug (DFD) capability for complex SoC and having DFDstandardization makes the Open Core Protocol (OCP) ...
Electronic Design

Get Acquainted with JTAG Basics

Download the PDF of this article. These days, hardware debug interfaces like the Joint Test Action Group (JTAG) IEEE 1149.1 standard are ubiquitous. You can find them on many microcontroller and ...
Embedded

Using an open debug interconnect model to simplify embedded systems design

Technology people are generally familiar with the Open SystemsInterconnection model for computer networks and protocols, oftenreferred to as the OSIReference Model (ISO 7498)[1].The Basic Reference ...
Electronic Design

Harness Robust Debugging Techniques To Improve Embedded Linux Systems

You can use Linux and still employ a methodology that includes all of the different phases of the ever-critical debugging process. A growing number of embedded developers are experimenting with the ...
Design-Reuse

Communication centric test and debug infrastructure for multi core SoC

The integration and debug of multiple cores, combined with an increasing ratio of overall gates vs. package IO, makes an increasingly dominant amount of a system design "“deeply embedded†, such ...
Design-Reuse

On-chip instrumentation aids OCP debugging

Leading embedded processor and intellectual property (IP) developers have adopted the Open Chip Protocol (OCP) socket as a standards-based approach to on-chip bus integration. An emerging capability ...
IT News For Australia Business

Intel debugger interface open to hacking via USB

Researchers from security vendor Positive Technologies have revealed that some new Intel processors contain a debugging interface accessible via USB 3.0 ports, that can be used to obtain full control ...